The present invention relates to a semiconductor memory device; and, more specifically, the invention relates to a memory cell array system capable of accessing (inputting and outputting) an ultra-large number of bits in a dynamic memory simultaneously.
In connection with various semiconductor memory devices that have been studied by the inventor of this invention, such as DRAMs, there have been growing demands on the memory chip for an increased number of bits to increase the effective band width (frequency.times.number of input/output bits) of the semiconductor memory system. However, it is not easy to realize an input/output width having an ultra-large bit number, more than 32 bits, such as 128 bits, while preventing an increase in the area of the chip. To realize this requires an improvement in the memory cell array.
A technique for constructing I/O lines in a hierarchical structure is disclosed in Japanese Patent Laid-Open No. 178158/1998, Japanese Patent Laid-Open No. 288888/1997, U.S. Pat. No. 5,657,286 (that corresponds to Japanese Patent Laid-Open No. 334985/1995) and U.S. Pat. No. 5,546,349 (that corresponds to Japanese Patent Laid-Open No. 8251/1997).